1. Field of the Invention
The present invention relates to semiconductor memories, and in particular, to redundancy therein.
2. Description of the Related Art
Semiconductor memories are generally organized in a two-dimensional array, wherein the memory elements are located at the intersection of rows and columns of the array. To access a given memory element, a word-line and bit-line are selected. For this purpose, memory addresses are typically divided into row and column address signals, which are decoded and used to select groups of memory cells for read or write access.
In the manufacture of semiconductor memories, defects are frequently encountered. Such defects typically affect a small number of memory elements in the memory. To prevent rejection of an entire chip due to the presence of a comparatively small number of defective memory elements and to increase manufacturing process yield, typical semiconductor memory designs provide redundant memory elements. Redundant memory elements are used as replacements for elements that, during testing of the memory device, are determined to be defective. Redundancy circuitry typically includes laser programmable fuses or other non-volatile memory elements suitable for storing address configurations corresponding to defective memory elements.
Some redundancy configurations provide row redundancy while others provide column redundancy. In many redundancy configurations, defective rows or columns must be disabled. Typically, to disable a defective row or column, redundancy circuits physically disconnect the defective row or column (e.g., by fusible links) or logically deselect the defective row or column (e.g., based on a defective row/column address stored in non-volatile memory). Unfortunately, both approaches have disadvantages. Physical disconnection typically requires definition of fusible links on array pitch and further requires disconnection (e.g., by laser zapping) of such fusible links without collateral damage to nearby circuits. Logical deselection typically requires disabling of certain decode paths. Unfortunately, the associated gate delays can adversely affect access time.
U.S. Pat. No. 5,495,445 to Proebsting discloses an improved redundancy scheme in which a redundant element is able to override a defective element without the need for physical disconnection or logical deselection. Proebsting's design segments complementary input/output (I/O) lines into a first segment coupled to main memory elements and a second segment coupled to a redundant memory element. Resistive elements couple the first and second segments of the complementary input/output (I/O) lines. Voltage drop across the resistive element allows the redundant memory element to override a defective element. When the redundant memory element is not selected, the resistive element has a negligible impact on delay because parasitic capacitance at redundant memory element coupling points on the second segment is minimal.
Unfortunately, the redundancy scheme disclosed by Proebsting is limited in two ways. First, only a single group of redundant elements, e.g., a single redundant column or a single redundant row, is available to replace defective columns or rows. As a result, in the configurations disclosed, only one defective row or column is replaceable per array or subarray. Furthermore, extension of the redundancy scheme to provide additional, but similarly configured and connected, redundant columns or rows would adversely affect capacitance at the redundant memory element coupling points. Second, in the configurations disclosed, a group of redundant elements, e.g., a redundant column or redundant row, necessarily shares common word-line or column select circuits with the main columns or rows for which it provides redundancy. As a result, in a memory array decomposed into subarrays representing distinct sets of rows or columns, a given redundant column (or row) is necessarily be dedicated to a single subarray. In short, the redundancy scheme disclosed by Proebsting is limited to single redundant column (or row) per array or subarray, and more than one defective column (or row) per array or subarray is not tolerated.